1. Field of the Invention
This invention relates to semiconductor devices, and more particularly to device structures and methods for providing self-aligned contacts for semiconductor devices having vertical structural features such as V-groove metal oxide semiconductor (V-MOS) devices.
2. Description of the Prior Art
In the art of semiconductor manufacturing the cost of semiconductor devices is directly related to the number of devices, and their related functions, which can be placed on a single semiconductor chip and also to the number and complexity of the manufacturing steps necessary to fabricate devices.
In the past, efforts to increase device density have been somewhat limited by photolithographic dimensional limitations. Recently, however, techniques have become available which enable dimensions of less than one micron to be used in photolithographic processing. Interest has also recently turned to the application of vertically integrated device structures. For example, the article "Grooves add new dimension to V-MOS structure and performance," by F. B. Jenne, Electronics, Aug. 18, 1977, pp. 100-106, discusses some aspects of V-MOS technology and illustrates various techniques for increasing effective device density through the use of V-MOS technology.
Semiconductor processing techniques which reduce the number of processing steps and/or their complexity are also useful to lower the cost of semiconductor devices by increasing product yield or by increasing density, when the number of critical mask alignment steps can be reduced. Thus, manufacturing processes which provide a high degree of self-aligning elements, i.e., process steps which do not require the alignment and associated alignment tolerances of photolithographic masks, can indirectly aid in the reduction of the cost of semiconductor devices.
Prior art techniques which use vertical processing in combination with self-aligning process steps include the following references.
The article, "VMOS ROM," by T. J. Rodgers et al, IEEE J. Solid-State Circuits, vol. SC-11, No. 5, October 1976, pp. 614-622, teaches a self-aligning diffusion technique at page 619 for ensuring diffused bit line conductivity around a V-grooved etched MOSFET. A single masking oxide layer is used for the diffusion and V-etch mask.
U.S. Pat. No. 4,065,783 to Ouyang uses a similar masking technique to define an ion-implanted MOSFET channel region and a V-groove etched structure.
U.S. Pat. No. 4,116,720 to Vinson uses a similar technique to define both a V-groove and a buried ion-implanted storage node for a dynamic memory cell.
The article, "Optimization of Nonplanar Power MOS Transistors," by K. P. Lisiak et al, IEEE Tr. Electron Devices, vol. ED-25, No. 10, October 1978, pp. 1229-34, teaches in FIG. 7 (d) a fully self-aligned VMOS vertical channel power transistor, but does not suggest the method by which such a device can be fabricated.
Copending U.S. patent application "Method for Providing Self-Aligned Conductor in a V-Groove Device," R. R. Garnache et al, Ser. No. 103,981 and filed Dec. 17, 1979, is also pertinent as it teaches a photolithographic masking technique for providing a self-aligned electrode formed at least partially within a V-groove on the surface of a semiconductor.
U.S. Pat. No. 4,003,036 to Jenne describes a VMOS single FET/capacitor memory cell of the type to which the preferred embodiment of the invention described here has been applied.